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5-1 eclipse: combining performance, density, and embedded ram preliminary updated 8/24/2000 eclipse family data sheet eclipse family device highlights flexible programmable logic .25u, 5 layer metal cmos process 2.5 v vcc, 2.5/3.3 v drive capable i/o 1.5 watts up to 4032 supercells up to 583,000 max system gates up to 512 i/o embedded dual port sram up to 36-2,304 bit dual port high performance sram blocks up to 82,900 ram bits ram/rom/fifo wizard for automatic configuration configurable and cascadable phase lock loop (pdll) 4 pll/dlls jitter<200 ps, lock time <10 us capture and lock range: 25 to 250 mhz programmable multiply/divide: 1x, 2x, 4x d evice h ighlights programmable i/o high performance enhanced i/o (eio): less than 3 ns tco programmable slew rate control programmable i/o standards lvttl, lvcmos, pci, gtl+, sstl2,and sstl3 8 independent i/o banks 3 register configuration: input, output, oe advanced clock network 9 global clock networks 1 dedicated 8 programmable 16 i/o (high drive) networks: 2 i/os per bank 20 quad-net networks: 5 per quadrant figure 1. embedded eclipse block diagram
2 preliminary 5-2 preliminary eclipse table 1. eclipse product family members quick works design software the turnkey quickworks package provides the most complete esp and fpga software solution from design entry to logic synthesis, to place and route to simulation. the packages provide a solution for designers who use third party tools from cadence, mentor, orcad, synopsys, viewlogic, veribest and other third-party tools for design entry, synthesis, or simulation. process data eclipse is fabricated on a .25u 5 layer metal cmos process. the core voltage is 2.5 volt vcc supply and 3.3 tolerant i/o with the addition of 3.3 volt vccio. eclipse is available in commercial, industrial, and mili- tary temperature grades. programmable logic architectural overview the eclipse features an enhanced supercell with an additional d flip-flop register and associated control logic. this advanced architectural approach, addresses today?s highly register intensive designs. QL6250 ql6325 ql6500 ql6600 max gates 248,160 320,640 488,064 583,008 logic array 40x24 48x32 64x48 72x56 logic cells 960 1,536 3,072 4,032 max flip-flops 2,688 4,302 7,488 9,600 max i/o 256 320 448 512 ram modules 20 24 32 36 ram bits 46,100 55,300 73,700 82,900 packages pqfp 208 208 bga (1.27mm) 516 516 516 516 bga (1.0mm) 484 484 484, 672 484, 672 fpbga (0.8mm) 280 280 280 280 d esign s oftware q uick w orks p rocess d ata p rogrammable l ogic a rchitectural o verview
5-3 preliminary eclipse table 2. performance standards the eclipse logic supercell structure, figure 2, is sim- ilar to the .35 mm quicklogic logic cell with the addition of a second register. both registers share clk, set and reset inputs. the second register has a two-to-one multiplexer controlling its input. the register can be loaded from the nz output or directly from a dedicated input. note: the input "pp" is not an "input" in the classical sense. it can only be tied high or low using default links only and is used to select which path "nz" or "ps" is used as an input to the register. all other inputs can be con- nected not only to "tiehi" and "tielo" but to multiple routing channels as well. the complete logic cell consists of two 6-input and gates, four two-input and gates, seven two-to-one multiplexers and two d flip-flop with asynchronous set and reset controls. the cell has a fan-in of 30 (including register control lines) and fits a wide range of functions with up to 17 simultaneous inputs. it has 6 outputs, 4 combinatorial and 2 registered. the high logic capacity and fan-in of the logic cell accom- modate many user functions with a single level of logic delay while other architectures require two or more levels of delay figure 2. eclipse supercell function description slowest speed grade fastest speed grade multiplexer 16:1 5 ns 2.8 ns parity tree 24 6 ns 3.4 ns 36 6 ns 3.4 ns counter 16 bit 250 mhz 450 mhz 32 bit 250 mhz 450 mhz fifo 128 x 32 155 mhz 280 mhz 256 x 16 155 mhz 280 mhz 128 x 64 155 mhz 280 mhz clock to out 4.5 ns 2.5 ns system clock 200 mhz 400 mhz qs a1 a2 a3 a4 a5 a6 os op b1 b2 c1 c2 ms d1 e1 np e2 d2 ns f1 f3 f5 f6 f2 f4 ps pp mp az oz qz nz fz q2z qc qr
5-4 preliminary eclipse ram modules the eclipse family includes multiple dual-port 2,304- bit ram modules for implementing ram, rom and fifo functions. each module is user-configurable into four different block organizations. modules can also be cascaded horizontally to increase their effec- tive width or vertically to increase their effective depth as shown in figure 3. the ram can also be configured as a modified harvard architecture, simi- lar to those found in dsps. figure 3. 2,304-bit quickram module the number of ram modules varies from 12 to 36 blocks within the eclipse family, for a total of 46.1k to 82.9k bits of ram. using two "mode" pins, designers can configure each module into 128 x 18 (mode 0), 256 x 9 (mode 1), 512 x 4 (mode 2), or 1024 x 2 blocks (mode 3). the blocks are also easily cascadable to increase their effective width and/or depth. see figure 4. figure 4. cascaded ram modules the ram modules are dual-port, with completely independent read and write ports and separate read and write clocks. the read ports support asynchronous and synchronous operation, while the write ports support synchronous operation. each port has 18 data lines and 10 address lines, allowing word lengths of up to 18 bits and address spaces of up to 1024 words. depending on the mode selected, however, some higher order data or address lines may not be used. the write enable (we) line acts as a clock enable for synchronous write operation. the read enable (re) acts as a clock enable for synchronous read opera- tion (asyncrd input low), or as a flow-through enable for asynchronous read operation (asyn- crd input high). designers can cascade multiple ram modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. a similar technique can be used to create depths greater than 512 words. in this case address signals higher than the ninth bit are encoded onto the write enable (we) input for write operations. the read data outputs are multiplexed together using encoded higher read address bits for the multiplexer select signals. the ram blocks can be loaded with data generated internally (typically for ram or fifo functions) or with data from an external prom (typically for rom functions). the ram achieve 155 mhz perfor- mance for the lowest speed grade devices when using multiple blocks cascaded together. ram m odules mode[1:0] wa[9:0] wd[17:0] we wclk 2,304-bit module asyncrd ra[9:0] rd[17:0] re rclk wdata rdata rdata waddr wdata raddr ram module (2,304 bits) ram module (2,304 bits)
5-5 preliminary eclipse multiple accessing of memories the extremely fast ram can be used in designs that require multiple memory accessing. the ram achieves 280 mhz performance for the fastest speed grade and 155 mhz performance for the lowest speed grade devices when using multiple blocks cas- caded together. write through of data is also possi- ble with the quicklogic ram. pll phase lock loops (plls), also known as frequency synthesizers, are used to create a master clock from a lower input frequency clock in dsps. there are four plls in the eclipse family, one is multiplexed with the dedicated clock and the remaining three connect to global clocks. the plls have a frequency range of 25mhz to 250mhz. frequency synthesis can also be created in increments of multiply by 2, 4 and divide by 2, 4. in addition, there is an early clock option to further reduce the tco of a system and a pll output option to drive external devices. a lock detect signal is provided to indicate a pll is in lock. figure 5. pll clock network m ultiple a ccessing of m emories pll
5-6 preliminary eclipse figure 6. pll block diagram pll features phase and frequency lock lock range: 25 mhz to 250 mhz jitter: < 200 ps across all ranges lock time: <200 steps or <10 us (which ever is less) early clock option for tco <= 3 ns no external components frequency multiply and divide @ 4x, 2x, 1x, 0.5x input frequency lock detect for system start-up phased locked output option @ 4x, 2x, 1x, 0.5x input frequency pll standby/bypass mode i/o cell structure eclipse features a variety of distinct i/o pins to maximize performance, functionality, and flexibility with bi-directional i/o pins and input-only pins. all input and i/o pins are 2.5v and 3.3v tolerant and comply with the specific i/o standard selected. the outputs swing from vss to vcci/o (0v to 3.3v 10%). the vcci/o pins must be tied to a 3.3v supply to provide 3.3v compliance. if 3.3v compliance is not required, then these pins must be tied to the 2.5v supply. eclipse can also support lvds and lvpecl i/o standards with the addition of an external resistor. table 3 summarizes the i/o specifications that will be supported. filter vco buf buf buf early clock delay clocktree frequency divide frequency multiply vco frequency range adjust and pll bypass fin fout match fout clock tree 1 2 1 2 + ? lock detect loop filter adjust delay pll reset phase detector 2 4 1 pll f eatures i/o c ell s tructure i/o standard reference voltage output voltage application lvttl n/a 3.3 general purpose lvcmos2 n/a 2.5 general purpose pci n/a 3.3 pci bus applications gtl+ 1 n/a high speed bus - pentium pro sstl3 1.5 3.3 memory bus - hitachi, ibm sstl2 1.25 2.5 memory bus - hitachi, ibm
5-7 preliminary eclipse table 3. i/o standards and applications as designs become more complex and requirements more stringent, varying i/o standards are developing for specific applications. i/o standards for proces- sors, memories and various bus applications have become common place and a requirement for many systems. in addition, i/o timing has become a greater issue with specific requirements for setup, hold, clock to out, and switching times. the eclipse family has addressed these changing sys- tem requirements. the eclipse family includes a com- pletely new i/o cell which consists of programmable i/os as well as a new cell structure consisting of 3 registers - input, output and output enable. eclipse will offer banks of programmable i/o that addresses many of the new bus standards that are popular today. in addition, the input register addresses the setup time; the output register addresses clock-to-out time; and the oe register addresses the switching time from high impedance to a given value. figure 7. eclipse i/o cell the bi-directional i/o pin options can be pro- grammed for input, output, or bi-directional opera- tion. as shown in figure 7, each bi-directional i/o pin is associated with an i/o cell which features an input/feedback register, an input buffer, output/feed- back register, three-state output buffer, an output enable register, and two (2) two-to-one multiplexers. for input functions, i/o pins can provide combinato- rial, registered data or both options simultaneously to the logic array. for combinatorial input operation, data is routed from i/o pins through the input buffer to the array logic. for registered input operation, i/ o pins drive the d input of input cell registers, allow- ing data to be captured with fast set-up times without consuming internal logic cell resources. for output functions, i/o pins can receive combina- torial or registered data from the logic array. for combinatorial output operation, data is routed from the logic array through a multiplexer to the i/o pin. for registered output operation, the array logic drives the d input of the output cell register which in turn drives the i/o pin through a multiplexer. the multi- plexer allows either a combinatorial or a registered signal to be driven to the i/o pin. the three-state output buffer controls the flow of data from the array logic to the i/o pin and allows the i/o pin to act as an input and/or output. the buffer ? s output enable can be individually controlled by a logic cell array or any pin (through the regular routing resources), or bank-controlled through one of the glo- bal networks. the signal can be also be either combi- natorial or registered. this is identical to that of the flow for the output cell. for combinatorial control operation data is routed from the logic array through a multiplexer to the three-state control. for regis- tered control operation, the array logic drives the d input of the oe cell register which in turn drives the three-state control through a multiplexer. the multi- plexer allows either a combinatorial or a registered signal to be driven to the three-state control. for out- put functions, i/o pins can be individually configured for active high, active low, or open-drain inverting operation. in the active high and active low modes, the pins of all devices are fully 3.3v compli- ant. when i/o pins are unused, the oe controls can be permanently disabled, allowing the output cell regis- ter to be used for registered feedback into the logic array. i/o cell registers are controlled by clock, clock enable, and reset signals, which can come from the regular routing resources, from one of the global net- works, or from two input pins per bank of i/o ? s. the clk and reset signals share a common line, while the clock enables for each register can be indepen- dently controlled. additionally the output and enable
5-8 preliminary eclipse registers will increase a device ? s register count. the addition of an output register will also decrease the tco. since the output register does not need to drive the routing the length of the output path is also reduced. extra registers add more inputs and outputs to the i/ o structure. extra routing resources are added to connect the i/o structure to the other parts of the device. i/o interface support is programmable on a per bank basis. there are 8 i/o banks per chip. users can not mix 2.5v i/o with 3.3v i/o on the same i/o bank. figure 5 illustrates the i/o bank configura- tions. each i/o bank is independent of other i/o bank and each i/o bank has it ? s own vccio and vref sup- plies. a mixture of different i/o standards can be used on the device, however there is a limitation as to which i/o standards can be supported within a given bank. differential i/o can be shared with non differ- ential i/o. there can only be one vref and one vccio per bank. figure 8. multiple i/o banks programmable slew rate each i/o has programmable slew rate capability. the rate is programmable to one of two slew rates either fast or slow. the slower rate can be used to reduce ground bounce noise. the slow slew rate is 1 v/ns under typical conditions. the fast slew rate will be 2.8 v/ns condition: 2.5v, 25c table 4. programmable slew rate programmable weak pull-down programmable weak-pull down resistor is available on each i/o. i/o weak pull-down eliminates the need for external pull down resistor for used i/o. the spec for pull-down current is maximum of 150ua under worst case condition. - 148ua @ 3.6v, -55c, - 69 ua@ 2.5v, 25c. figure 9. i/o weak pull-down i/o bank 0 i/o bank 1 i/o bank 4 i/o bank 5 i/o bank 7 i/o bank 6 i/o bank 2 i/o bank 3 vccio 0 vccio 1 vccio 5 vccio 4 vccio 7 vccio 6 vccio 2 vccio 3 vref 0 vref 1 vref 5 vref 4 vref 7 vref 6 vref 2 vref 3 vccio = 3.3v fast slew slow slew rising edge 2.8 v/ns 1.0 v/vs falling edge 2.86 v/ns 1.0 v/ns vccio = 2.5v fast slew slow slew rising edge 1.7 v/ns 0.6 v/vs falling edge 1.9 v/ns 0.6 v/ns p rogrammable s lew r ate p rogrammable w eak p ull -d own
5-9 preliminary eclipse clock networks global clocks there are 8 global clock networks in the eclipse device family. global clocks can drive logic cell, i/o, and ram registers in the device. three global clocks will each have access to a pll. five global clocks will have access to a quad net (local clock network) con- nection with a programmable connection to the reg- ister inputs. figure 10. global clock methodology quad-net network there are 5 quad-net local clock networks in each quadrant for a total of 20 in a device. each quad-net is local to a quadrant. quad-net is multiplexed with the clock buffer before driving the column clock buffers. dedicated clock there is one dedicated clock in the eclipse device family. it connects to the clock input of the supercell, i/o and ram registers through a hardwired connection and is multiplexed with the programmable clock input. there are four inversions from pad to register inputs and the dedicated clock takes on the same configuration as the global clock. the dedicated clock provides a fast global network with low skew. the dedicated clock has access to one of four pll ? s. you have the ability to select either the dedicated clock or the programmable clock, figure 11. the performance of the dedicated clock is given in table 5. figure 11. dedicated clock circuitry within logic cell table 5. dedicated clock performance c lock n etworks clock performance tt, 25c, 2.5v global dedicated macro (near) 1.51 ns 1.59 ns i/o (far) 2.06 ns 1.73 ns skew 0.55 ns 0.14 ns clk programmable clock hard-wired clock
5-10 preliminary eclipse i/o control and local hi-drives each bank of i/o ? s has 2 input only pins that can be programmed to drive the rst, clk and en inputs of i/o ? s in that bank. these input only pins also double up as high drive inputs to a quadrant. both as an i/o control or high drive, these buffers can be driven by the internal logic. the performance is indicated in table 6. table 6. i/o control network/local high-drive programmable logic routing six types of routing resources are provided, as in the quickram devices: short (sometimes called seg- mented) wires, dual wires, quad wires, express wires, distributed networks and defaults. short wires span the length of 1 logic cell, always in the vertical direc- tion. dual wires run horizontally and span the length of 2 logic cells. short and dual wires are predomi- nantly used for local connections. they effectively traverse one or two logic cells utilize an interconnect element to continue to the next cell or to change direction. quad wires have passive link interconnect elements every fourth logic cell. as a result, these wires are typically used to implement intermediate length or medium fan-out nets. express lines run the length of the programmable logic uninterrupted. each of these lines has a higher capacitance than a quad, dual or short wire, but less capacitance than shorter wires connected to run the length of the device. the resistance will also be lower because the express wires don ? t require the use of "pass" links. express wires provide higher perfor- mance for long routes or high fan-out nets. distributed networks are described in the clock/ control section. these wires span the programmable logic, and are driven by "column clock" buffers. each dedicated clock network pin buffer is hard wired to a set of column clock buffers. five global networks "global buffers" can be connected through special purpose routing called "hsck lines" to either a dedi- cated pin buffer, or any vertical routing wire crossing it. global por (power-on reset) the eclipse family of devices features a global power- on reset. this reset will be hardwired to all registers and will reset the registers upon power-up of the device. the circuitry used to support the global por is similar to the power-up loading circuitry. figure 12. power-on reset separate power and logic-cell power to decrease the logic cell area and to eliminate the need for disable transistors in the input stage of the logic cell, a separate power supply for the logic cells has been added to the family. this supply will be grounded during programming and for various test modes. tt, 25c, 2.5v from pad from array i/o (slow) 1.00ns 1.14ns i/o (fast) 0.63ns 0.78ns skew 0.37ns 0.36ns p rogrammable l ogic r outing g lobal por ( power - on reset ) vcc power-on reset q xxxxxxx 0 s eparate p ower and logic - cell power s eparate p ower and logic - cell power
5-11 preliminary eclipse ieee standard 1149.1a. the eclipse family of devices supports ieee standard 1149.1a. the following public instructions are supported: bypass, extest, and sample/preload. two additional modes ramwt and ramrd can be used to load the ram. the pin functions will be the same as in the quickram family. figure 13. jtag block diagram jtag bsdl support bsdl-boundary scan description language machine-readable data for test equipment to generate testing vectors and software bsdl files available for all device/ package combinations from quicklogic extensive industry support available and atg (automatic test-vector generation) security fuses. there are two security links, one to disable reading from the array, the other to disable jtag. flexibility fuse. the flexibility link is actually implemented as two "default" links. if the tie-low link is programmed, ram power up loading (from an external eprom) is enabled, which might affect jtag. if the tie-hi link is programmed, ram power-up loading (from an exter- nal eprom) will be disabled. jtag will work nor- mally, and can also be used to load the ram. ieee s tandard 1149.1 a .
5-12 preliminary eclipse packaging eclipse product will be offered in the following packages. military temperature range plastic packages will be added as follow on products to the commercial and industrial products. table 7. packaging options pin count 208 280 484 516 672 package style pqfp fb bga bga bga bga pitch 0.8mm 1.0mm 1.27mm 1.00mm ordering code pq208 pt280 ps484 pb516 ps672 QL6250 x x x x ql6325 x x x x ql6500 x x x x ql6600 x x x x

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